1. Field
Various embodiments of the present invention relate to a semiconductor device that performs a boot-up operation.
2. Description of the Related Art
A variety of semiconductor devices, such as a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), and a memory device, use a fuse to store information required for operation thereof. The information may include setting information and repair information. Programming a laser fuse is accomplished by cutting the laser fuse with a laser. This means that the fuse may be programmed only in the wafer state and is incapable of being programmed after the wafer is packaged. An e-fuse (i.e., an electrical fuse) may be used to overcome the limitations of the laser fuse. An e-fuse uses a transistor that stores data by changing the resistance between the gate and the drain/source.
FIG. 1 is a diagram illustrating an e-fuse implemented with a transistor that operates as a resistor or capacitor.
Referring to FIG. 1, the e-fuse includes a transistor T having a gate G receiving a power supply voltage and a drain/source D/S receiving a ground voltage.
When a normal power supply voltage, which is tolerable to the transistor T, is applied to the gate G, the e-fuse operates as a capacitor C. Thus, there is no current flowing between the gate G and the drain/source D/S. However, when a high power supply voltage, which is intolerable to the transistor T, is applied to the gate G, the gate oxide of the transistor T is destroyed. Accordingly, the gate G and the drain/source D/S may be shorted such that the e-fuse operates as a resistor R. In this case, current flows between the gate G and the drain/source D/S.
The data of the e-fuse is recognized through the resistance between the gate G and the drain/source D/S of the e-fuse. To recognize the data of the e-fuse, two methods are used. First, the data of the e-fuse may be recognized directly without performing an additional sensing operation by increasing the size of the transistor T. Second, the data of the e-fuse may be recognized by sensing current flowing through the transistor T using an amplifier. However, these two methods have restrictions on circuit area because the transistor T is designed to be large in size or the additional amplifier needs to be provided for each e-fuse.
U.S. Pat. No. 7,269,047 has disclosed a method for reducing the circuit area occupied by e-fuses by forming the e-fuses in an array.
FIG. 2 is a diagram illustrating a conventional cell array 200 implemented with e-fuses.
Referring to FIG. 2, the cell array 200 includes memory cells 201 to 216 arranged in N rows and M columns. The memory cells 201 to 216 include memory elements M1 to M16 and switch elements S1 to S16, respectively. For example, a memory cell 201 includes a to memory element M1 and a switching element S1. The memory elements M1 to M16 are e-fuses having the properties of resistors or capacitors, depending on whether the e-fuses are ruptured. That is, the e-fuses M1 to M16 may be considered as resistive memory elements to store data according to the amount of resistance. The switch elements S1 to S16 electrically couple the memory elements M1 to M16 to the column lines BL1 to BLM, respectively, under the control of row lines WLR1 to WLRN.
Hereafter, suppose that the second row and the M-th column are selected, that is, the memory cell 208 is a selected memory cell. Voltages applied to the selected memory cell 208 and the unselected memory cells 201 to 207 and 209 to 216 during program and read operations will be described.
Program Operation
The row line WLR2 of the selected row is activated, and the other row lines WLR1 and WLR3 to WLRN are deactivated. Thus, the switch elements S5 to S8 are turned on, and the switch elements S1 to S4 and S9 to S16 are turned off. At this time, a high program voltage that may break the gate oxide of a transistor (i.e., a memory element) is applied to a program/read line WLP2 of the selected row, and a low-level voltage, for example, ground voltage, is applied to the other program/read lines WLP1 and LWP3 to WLPN. In general, the program voltage is a high voltage generated by a charge pumping method using a power supply voltage. The selected column line BLM to is coupled to a data access circuit (not shown), and the unselected column lines BL1 to BLM-1 float. The data access circuit drives the selected column line BLM to a logic low level to program (or rupture) the memory element M8 of the selected memory cell 208 when input data is program data, for example, ‘1’. Meanwhile, the data access circuit drives the selected column line BLM to a logic high level to prevent the memory element M8 of the selected memory cell 208 from being programmed when the input data is not program data, for example, ‘0’. Since the unselected column lines BL1 to BLM-1 float, the memory elements M5 to M7 are not programmed even though a high voltage is applied to the gates thereof.
Read Operation
The row line WLR2 of the selected row is activated, and the other row lines WLR1 and WLR3 to WLRN are deactivated. Thus, the switch elements S5 to S8 are turned on, and the switch elements S1 to S4 and S9 to S16 are turned off. At this time, a read voltage, for example, a power supply voltage, suitable for a read operation is applied to the program/read line WLP2 of the selected row, and a low-level voltage, for example, ground voltage, is applied to the other program/read lines WLP1 and LWP3 to WLPN. The selected column line BLM is coupled to the data access circuit, and the unselected column lines BL1 to BLM-1 are floated. When current flows through the selected column line BLM, the data access circuit recognizes that the memory element M8 is programmed, that is, the data access circuit recognizes the data of the memory cell 208 as ‘1’. On the other hand, when no current flows through the selected column line BLM, the data access circuit recognizes that the memory element M8 is not programmed, that is, the data access circuit recognizes the data of the memory cell 208 as ‘0’.
FIG. 2 illustrates that one column line BLN is selected among the column lines BL1 to BLN. However, several column lines may be selected at once. That is, several memory cells belonging to one row may be simultaneously programmed or read.
FIG. 3 is a block diagram illustrating an e-fuse array circuit 300 including the cell array 200 shown in FIG. 2.
Referring to FIG. 3, the e-fuse array circuit 300 includes the cell array 200 shown in FIG. 2, a row circuit 310, a column decoder 320, and a data access circuit 330.
The row circuit 310 controls the row lines WLR0 to WLR and the program/read lines and allows the above-described program and read operations to be performed. A row address ROW_ADD inputted to the row circuit 310 designates a row selected among a plurality of rows, a program signal PGM directs a program operation, and a read signal RD directs a read operation.
The column decoder 320 electrically couples a column line, selected by the address COL_ADD among the column lines BL1 to BLM, to the data access circuit 330. FIG. 3 exemplarily illustrates that eight column lines are simultaneously selected among the column lines BL1 to BLM.
The data access circuit 330 performs data access operations on the column lines selected by the column decoder 320. During a program operation, the data access circuit 330 controls the selected column lines to be programmed or non-programmed according to input data DATA<0> to DATA<7>. During a read operation, the data access circuit 330 senses whether current flows through the selected column lines and outputs the sensed results as output data DATA<0> to DATA<7>.
FIG. 4 is a diagram illustrating a conventional memory device in which the e-fuse array circuit 300 is included.
Referring to FIG. 4, the memory device includes a plurality of memory banks BK0 to BK3, a plurality of registers 410_0 to 410_3, a resistor 4104, a setting circuit 420, and the e-fuse array circuit 300. The plurality of registers 410_0 to 410_3 are provided for the respective memory banks BK0 to BK3 to store repair information, and the register 410_4 stores setting information.
The e-fuse array circuit 300 stores repair information used in the memory banks BK0 to BK3, for example, addresses of defective memory cells included in the memory banks BK0 to BK3. Furthermore, the e-fuse array circuit 300 stores setting information required for the operation of the memory device.
The registers 410_0 to 410_3 provided for the respective memory banks BK0 to BK3 store the repair information of the corresponding memory banks. For example, the register 410_0 stores the repair information of the memory bank BK0, and the register 410_2 stores the repair information of the memory bank BK2. Furthermore, the register 4104 stores setting information to be used in the setting circuit 420.
The setting circuit 420 may set various setting values required for operation of the memory device, using the setting information stored in the register 410_4. For example, the setting circuit 420 may set an internal voltage level and various latencies. The information stored in the registers 410_0 to 410_4 is maintained only while power is supplied. The repair information and the setting information to be stored in the registers 410_0 to 410_4 are received from the e-fuse array circuit 300. The e-fuse array circuit 300 transmits the stored repair information and setting information to the registers 410_0 to 410_4 when a boot-up signal BOOTUP is activated.
Since the e-fuse array circuit 300 is configured in an array, a predetermined processing time is required to call data stored in the e-fuse array circuit 300. Since the data may not be called immediately, a repair operation or setting operation by directly using the data stored in the e-fuse array circuit 300 may not be performed. Thus, the repair information and the setting information stored in the e-fuse array circuit 30 are transmitted and stored into the registers 410_0 to 410_4, and the data stored in the registers 410_0 to 410_4 are used for the repair operation of the memory banks BK0 to BK3 and the setting operation of the setting circuit 420. The process of transmitting the repair information and the setting information stored in the e-fuse array circuit 300 to the registers 410_0 to 410_4 is referred to as a boot-up operation. Only after the boot-up operation is completed may the memory device repair a defective memory cell and perform various setting operations. Then, the memory device may start a normal operation.
Since the internal components of the memory device, that is, the memory banks BK0 to BK3 and the setting circuit 420, are operated by receiving the information required for operation from the e-fuse array circuit 300, the internal components may operate with optimal setting values. However, since it is impossible for the e-fuse array circuit 300 to operate with optimal setting values, a stable operation of the e-fuse array circuit 300 may not be guaranteed.